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AT24C32/64
Pin Description
Memory Organization
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each
EEPROM device and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is
open-drain driven and may be wire-ORed with any number of other open-drain or open
collector devices.
DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device address
inputs that are hard wired or left not connected for hardware compatibility with
AT24C16. When the pins are hardwired, as many as eight 32K/64K devices may be
addressed on a single bus system (device addressing is discussed in detail under the
Device Addressing section). When the pins are not hardwired, the default A 2 , A 1 , and A 0
are zero.
WRITE PROTECT (WP): The write protect input, when tied to GND, allows normal write
operations. When WP is tied high to V CC , all write operations to the upper quandrant
(8/16K bits) of memory are inhibited. If left unconnected, WP is internally pulled down to
GND.
AT24C32/64, 32K/64K SERIAL EEPROM: The 32K/64K is internally organized as 256
pages of 32 bytes each. Random word addressing requires a 12/13 bit data word
address.
3
0336K–SEEPR–7/03
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